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GTL2000/GTL2002/ GTL2010
GND SREF S1 S2 S3 S4 S5 S6 S7 S8 S9 1 2 3 4 5 6 7 8 9 10 48 47 46 45 44 43 42 41 40 39 GREF DREF D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22
Bi-directional low voltage translators
GTL2002
GTL2010
Semiconductors
Description
The Philips family of Gunning Transceiver Logic (GTL) Bi-Directional Low Voltage Translators are used for high-speed translation between different voltage levels with low ON-state resistance and minimal propagation delay. Unlike level shifting bus switches, which are limited to translation between two fixed voltages (e.g. 5 V and 3.3 V), the 22-bit GTL2000, 2-bit GTL2002, and 10-bit GTL2010 can translate any voltage between 1 V and 5 V to any other voltage between 1 V and 5 V. The devices provide NMOS pass transistors (Sn and Dn pins) with a common gate (GREF pin) and a reference transistor (SREF and DREF pins). When one of the Sn or Dn ports are low, the clamp is in the ON-state and the Sn and Dn ports are connected through a low ON-resistance connection. Assuming the higher voltage is applied on the Dn port: * when the Dn port is high, the voltage on the Sn port is limited to the voltage set by SREF * when the Sn port is high, the Dn port is pulled to a higher voltage by a pull up resistor This functionality allows a seamless translation between higher and lower voltages selected by the user, without the need for directional control signals. All transistors have the same electrical characteristics and deviation from one output to another in voltage or propagation delay is minimal. This is a benefit over discrete transistor voltage translation.The translator's transistors also provide excellent ESD protection to lower voltage devices and protects less ESD resistant devices.
11
GTL2000
38 37 36 35 34 33 32 31 30 29 28 27 26 25
S10 12 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 13 14 15 16 17 18 19 20 21 22 23 24
Features
* * * * * * No directional control required for bi-directional voltage translations Low 6.5 RON resistance between input and output pins (Sn/Dn) 1.5 ns typical propagation delay 7.5 pF channel off-state capacitance Very low 5 A stand-by current No power supply required - Will not latch up
Ordering information
Package Container Tube SO T&R Tube SSOP T&R Tube TSSOP T &R HVQFN T &R GTL2000 NA NA GTL2000DL GTL2000DL-T GTL2000DGG GTL2000DGG-T NA GTL2002 GTL2002D GTL2002D-T NA NA NA GTL2002DP-T NA GTL2010 NA NA NA NA GTL2010PW GTL2010PW-T GTL2010BS-T
Applications
Any application that requires bi-directional or unidirectional voltage level translation from any voltage between 1.0 V & 5.0 V to any voltage between 1.0 V & 5.0 V * The open drain construction with no directional control is ideal for bi-directional low voltage (e.g., 1.0 V, 1.2 V, 1.5 V, or 1.8 V) processor I2C port voltage level translation to legacy 3.3 V and/or 5.0 V I2C bus signal levels at speeds up to 3.4 MHz. * Shifting processor sideband I/O signals from GTL / GTL+ voltage levels to LVTTL / TTL signal levels. *
In Europe and Asia, add ", 112" for tube orders and substitute ", 118" for "-T" for tape and reel orders (e.g., GTL2010PW, 112 and GTL2010PW, 118).
GTL2000/GTL2002/GTL2010
Bi-directional low voltage translators
w w w. s e m i c o n d u c t o r s . p h i l i p s . c o m
Typical bi-directional voltage translation
1.8 V 1.5 V 1.2 V 1.0 V VCORE CPU I/O S2 D2 GTL2002 GND SREF S1 GREF DREF D1 CHIPSET I/O VCC 200 K 5V TOTEM POLE OR OPEN DRAIN I/O
INCREASE BITSIZE BY USING 10 BIT GTL2010 OR 22 BIT GTL2000
3.3 V
VCC S3 S4 S5 Sn D3 D4 D5 Dn CHIPSET I/O
Bi-directional voltage translation
For the bi-directional clamping configuration, the GREF input must be connected to DREF and both pins must be pulled to high side VCC through a pull-up resistor (typically 200 k). A filter capacitor on DREF is recommended. The CPU output can be totem pole or open drain (pull up resistors may be required) and the chipset output can be totem pole or open drain (pull up resistors are required to pull the Dn outputs to VCC). However, if either output is totem pole, data must be uni-directional or the outputs must be 3-stateable and the outputs must be controlled by some direction control mechanism to prevent high to low contentions in either direction. If both outputs are open drain, no direction control is needed. The opposite side of the reference transistor (SREF) is connected to the CPU power supply voltage. When DREF is connected through a 200 k resistor to VCC and SREF is set between 1.0 V to VCC - 1.5 V, the output of each Sn has a maximum output voltage equal to SREF and the output of each Dn has a maximum output voltage equal to the pull up resistor voltage (e.g., 3.3 V and/or 5 V). Additional technical information can be found in Application Note AN10145 Bi-Directional Voltage Translators at: www.semiconductors.philips.com/logic/support/appnotes/specialty
Down voltage translation only
The reference transistor is connected the same as for the bi-directional translation. Pull up resistors are required if the chipset I/O are open drain.
Up voltage translation only
The reference transistor is connected the same way as for the bi-directional translation. A pull-up resistor is required on the higher voltage side (Dn) to get the full high level, since the translator will only pass the reference source voltage (SREF) as a high when doing an up translation. The driver on the lower voltage side only needs pull-up resistors if it is open drain.
Philips Semiconductors
Philips Semiconductors is a worldwide company with over 100 sales offices in more than 50 countries. For a complete up-to-date list of our sales offices please e-mail sales.addresses@www.semiconductors.philips.com. A complete list will be sent to you automatically. You can also visit our website http://www.semiconductors.philips.com/sales
(c) Koninklijke Philips Electronics N.V. 2003
All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: June 2003 document order number: 9397 750 11529
Published in U.S.A.

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